Regviz

Nordic Semiconductor /nrf52810 /PPI /CHENCLR

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Interpret as CHENCLR

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https://regviz.com/r/Nordic Semiconductor/nrf52810/PPI/CHENCLR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disabled)CH0 0 (Disabled)CH1 0 (Disabled)CH2 0 (Disabled)CH3 0 (Disabled)CH4 0 (Disabled)CH5 0 (Disabled)CH6 0 (Disabled)CH7 0 (Disabled)CH8 0 (Disabled)CH9 0 (Disabled)CH10 0 (Disabled)CH11 0 (Disabled)CH12 0 (Disabled)CH13 0 (Disabled)CH14 0 (Disabled)CH15 0 (Disabled)CH16 0 (Disabled)CH17 0 (Disabled)CH18 0 (Disabled)CH19 0 (Disabled)CH20 0 (Disabled)CH21 0 (Disabled)CH22 0 (Disabled)CH23 0 (Disabled)CH24 0 (Disabled)CH25 0 (Disabled)CH26 0 (Disabled)CH27 0 (Disabled)CH28 0 (Disabled)CH29 0 (Disabled)CH30 0 (Disabled)CH31

CH25=Disabled, CH20=Disabled, CH1=Disabled, CH30=Disabled, CH3=Disabled, CH24=Disabled, CH26=Disabled, CH23=Disabled, CH5=Disabled, CH0=Disabled, CH10=Disabled, CH31=Disabled, CH18=Disabled, CH15=Disabled, CH9=Disabled, CH4=Disabled, CH12=Disabled, CH13=Disabled, CH11=Disabled, CH14=Disabled, CH7=Disabled, CH19=Disabled, CH27=Disabled, CH22=Disabled, CH21=Disabled, CH2=Disabled, CH29=Disabled, CH8=Disabled, CH6=Disabled, CH16=Disabled, CH28=Disabled, CH17=Disabled

Description

Channel enable clear register

Fields

CH0

Channel 0 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH1

Channel 1 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH2

Channel 2 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH3

Channel 3 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH4

Channel 4 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH5

Channel 5 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH6

Channel 6 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH7

Channel 7 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH8

Channel 8 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Enabled): Read: channel enabled

1 (Clear): Write: disable channel
CH9

Channel 9 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH10

Channel 10 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH11

Channel 11 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH12

Channel 12 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH13

Channel 13 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH14

Channel 14 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH15

Channel 15 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH16

Channel 16 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Enabled): Read: channel enabled

1 (Clear): Write: disable channel
CH17

Channel 17 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH18

Channel 18 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH19

Channel 19 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH20

Channel 20 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH21

Channel 21 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH22

Channel 22 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH23

Channel 23 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH24

Channel 24 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH25

Channel 25 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH26

Channel 26 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH27

Channel 27 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH28

Channel 28 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH29

Channel 29 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH30

Channel 30 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled
CH31

Channel 31 enable clear register. Writing ‘0’ has no effect

0 (Disabled): Read: channel disabled

1 (Clear): Write: disable channel

1 (Enabled): Read: channel enabled

Links

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Register License

Copyright © 2010 - 2021, Nordic Semiconductor ASA All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

  3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data